The Field Effect Transistor
The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals.
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET a small amount of voltage is applied to the gate in order to control current flowing between the source and drain. In FETs the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal, enlarging or constricting the channel and thereby controlling the current flowing between the source and the drain.
FIG. 1 illustrates a FET 100 comprising a p-type substrate, and two spaced-apart n-type diffusion areas—one of which will serve as the “source”, the other of which will serve as the “drain” of the transistor. The space between the two diffusion areas is the “channel”. A thin dielectric layer is disposed over the substrate in the neighborhood of the channel, and a “gate” structure is disposed over the dielectric layer atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) Electrical connections (not shown) may be made to the source, the drain, and the gate. The substrate may be grounded.
Generally, when there is no voltage on the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain, and can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
The Floating Gate Transistor
A floating gate transistor is generally a transistor structure, broadly based on the FET, as described hereinabove. As illustrated in FIG. 2, the floating gate transistor 200 has a source and a drain, but rather than having only one gate, it has two gates which are called control gate (CG) and floating gate (FG). It is this arrangement of control gate and floating gate which enables the floating gate transistor to function as a memory cell, as described hereinbelow.
The floating gate is disposed over tunnel oxide (comparable to the gate oxide of the FET). The floating gate is a conductor, the tunnel oxide is an insulator (dielectric material). Another layer of oxide (interpoly oxide, also a dielectric material) separates the floating gate from the control gate.
Since the floating gate is a conductor, and is surrounded by dielectric material, it can store a charge. Electrons can move around freely within the conductive material of the floating gate (which comports with the basic definition of a “conductor”).
Since the floating gate can store a charge, it can exert a field effect on the channel region between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove. Mechanisms for storing charges on the floating gate structure, as well as removing charges from the floating gate are described hereinbelow.
Generally, if a charge is stored on the floating gate, this represents a binary “1”. If no charge is stored on the floating gate, this represents a binary “0”. (These designations are arbitrary, and can be reversed so that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how a floating gate memory cell operates. The other half is how to determine whether there is a charge stored on the floating gate—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the source, drain and gate terminals, and determining how conductive the channel is. Some modes of operation for a floating gate memory cell are described hereinbelow.
Normally, the floating gate non-volatile memory (NVM) cell has only a single “charge-storing area”—namely, the conductive floating gate (FG) structure, and can therefore only store a single bit of information (binary “1” or binary “0”). More recently, using a technology referred to as “multi-level cell” (MLC), two or more bits can be stored in and read from the floating gate cell.
A Two-Bit (Dual Bit) Memory Cell
Another type of memory cell, called a “nitride, read only memory” (NROM) cell, has a charge-storage structure which is different from that of the floating gate memory cell and which permits charges to be stored in two separate charge-storage areas. Generally, the two separate charge storage areas are located within a non-conductive layer disposed between the gate and the underlying substrate, such as a layer of nitride formed in an oxide-nitride-oxide (ONO) stack underneath the gate. The non-conductive layer acts as a charge-trapping medium. Generally, electrical charges will stay where they are put in the charge-trapping medium, rather than being free to move around as in the example of the conductive floating gate of the floating gate memory cell. A first bit of binary information (binary “1” or binary “0”) can be stored in a first portion (such as the left-hand side) of the charge-trapping medium, and a second bit of binary information (binary “1” or binary “0”) can be stored in a second portion (such as the right-hand side) of the charge-trapping medium. An alternative viewpoint is that different charge concentrations can be considered for each bit of storage. Using MLC technology, at least two bits can be stored in and read from each of the two portions (charge storage areas) of the charge-trapping medium (for a total of 4 bits), similarly 3 bits or more than 4 bits may be identified.
FIG. 3 illustrates a basic NROM memory cell, which may be viewed as an FET with an “ONO” structure (or layer, or stack) inserted between the gate and the substrate. (One might say that the ONO structure is “substituted” for the gate oxide of the FET.)
The ONO structure is a stack (or “sandwich”) of lower oxide 322, a charge-trapping material such as nitride 324, and an upper oxide 326. The ONO structure may have an overall thickness of approximately 10-25 nm, such as 18 nm, as follows:                the bottom oxide layer 322 may be from 3 to 6 nm, for example 4 nm thick;        the middle nitride layer 324 may be from 3 to 8 nm, for example 4 nm thick; and        the top oxide layer 326 may be from 5 to 15 nm, for example 10 nm thick.        
The NROM memory cell has two spaced apart diffusions 314 and 316 (which can function as source and drain, as discussed hereinbelow), and a channel region 320 defined in the substrate between the two diffusion regions 314 and 316.
In FIG. 3, the diffusions are labeled “N+”. This means that they are regions in the substrate that have been doped with an electron donor material, such as phosphorous or arsenic. These diffusions are typically created in a larger region which is p-type cell well (CW) is doped with boron (or indium). This is the normal “polarity” for a NVM cell employing electron injection (which may also employ hole injection, such as for erase). With opposite polarity (phosphorus or arsenic implants in a n-type cell well), the primary injection mechanism would be for holes, which is generally accepted to be not as effective as electron injection. One skilled in the art will recognize that the concepts disclosed herein can be applied to opposite polarity devices.
The charge-trapping material 324 is non-conductive, and therefore, although electrical charges can be stored in the charge-trapping material, they are not free to move around, they will generally stay where they are stored. Nitride is a suitable charge-trapping material. Charge trapping materials other than nitride may also be suitable for use as the charge-trapping medium. One such material is silicon dioxide with buried polysilicon islands. A layer (324) of silicon dioxide with polysilicon islands would be sandwiched between the two layers of oxide (322) and (326). Alternatively, the charge-trapping layer 324 may be constructed by implanting an impurity, such as arsenic, into a layer of silicon dioxide deposited on top of the bottom oxide 322.
The memory cell 300 is generally capable of storing at least two bits of data—at least one right bit(s) in a first storage area of the nitride layer 324 represented by the dashed circle 323, and at least one left bit(s) in a second storage area of the nitride layer 324 represented by the dashed circle 321. Thus, the NROM memory cell can be considered to comprise two “half cells”, each half cell capable of storing at least one bit(s). The storage areas 321, 323 may variously be referred to as “charge storage areas”, “charge trapping areas”, and the like, throughout this document. It should be understood that a half cell is not a physically separate structure from another half cell in the same memory cell. The term “half cell”, as it may be used herein, is used herein only to refer to the “left” or “right” bit storage area of the ONO stack (nitride layer).
Each of the storage areas 321, 323 in the charge-trapping material 324 can exert a field effect on the channel region 320 between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove (FIG. 2). Some mechanisms for injecting charges (either electrons or holes) in the storage areas of the charge-trapping material, as well as removing charges from the storage areas of the charge-trapping material are described hereinbelow. The charge storage area 321 is generally above the diffusion 314, and the charge storage area 323 is generally above the diffusion 316.
Generally, if a charge is stored in a given storage area of the charge-trapping material, this represents a binary “1”, and if no charge is stored in a given storage area of the charge-trapping material, this represents a binary “0”. (Again, these designations are arbitrary, and can be reversed to that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how an NROM memory cell operates The other half is how to determine whether there is a charge stored in a given storage area of the charge-trapping material—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the diffusion regions (functioning as source and drain) and gate terminals, and determining how conductive the channel is. Some modes of operation for an NROM memory cell are described hereinbelow.
Generally, one feature of NROM cells is that rather than performing “symmetrical” programming and reading, NROM cells are beneficially programmed and read “asymmetrically”, which means that programming and reading occur in opposite directions. The arrows labeled in FIG. 3 are arranged to illustrate this point. Programming may be performed in what is termed the “forward” direction and reading may be performed in what is termed the “opposite” or “reverse” direction. Some programming and reading modes of operation for memory cells are described hereinbelow.
Programming, Erasing, and Reading the Floating Gate Memory Cell
FIG. 2A illustrates a technique for programming a floating gate memory cell, using channel hot electron (CHE) injection to put charges (inject electrons) into the floating gate. The floating gate memory cell generally comprises a channel region between a source region and a drain region, and a floating gate disposed between the channel region and the control gate (compare FIG. 2). This figure illustrates various voltages which may be applied to the source (Vs), to the gate (Vg) and to the drain (Vd), from external sources and/or connections (not shown). Generally, there is no “connection” to the floating gate.
Generally, in order implement CHE injection of electrons into the floating gate, the source is grounded, the drain is set to zero or to a positive voltage (which will “attract” electrons from the source, laterally across the channel region), and the gate is also set to a positive voltage (which will “attract” electrons vertically through the tunnel oxide, into the floating gate). As electrons flow through the channel from source to drain, some of the electrons will make their way through the tunnel oxide and become stored on the floating gate. This injection of electrons into the floating gate increases the threshold voltage of the memory cell. The shift (increase) in threshold voltage can be on the order of 3 or more volts. The threshold voltage (Vt) of the memory cell can later be measured, or “read”.
FIG. 2B illustrates a technique for erasing a floating gate memory cell, using a mechanism which is called “Fowler-Nordheim Tunneling”, abbreviated as “F-N tunneling”, or “FN tunneling”, or simply “FNT”.
Generally, whereas CHE injection was used (described hereinabove), in programming, to inject electrons into the floating gate, F-N tunneling (FNT) is used, in the erase operation, to remove electrons from the floating gate.
Generally, in order implement F-N tunneling of removing electrons from the floating gate, both the source and the drain are set to a positive voltage (to “attract” electrons through the tunnel oxide from the floating gate into the substrate), and the gate is set to a negative voltage (to “repel” electrons through the tunnel oxide from the floating gate into the substrate). This removal of electrons from the floating gate decreases the “threshold voltage” of the memory cell.
Generally, during programming, the threshold voltages of individual memory cells or (in the case of NROM, the two charge-storage areas of a single memory cell) are individually manipulated to represent the data desired to be stored. In contrast thereto, generally, during erase, it is normally acceptable to simply decrease the threshold voltages of a great many memory cells, all at once, such as all of the memory cells in a sector or block of a memory array.
Typically, to inhibit erase of selected memory cells, an “inhibit” signal, such as a positive voltage (which will not “repel” the electrons) may be applied to the gates of the selected memory cells. In a common array architecture, the gates of several memory cells are typically all connected to a common word line (of many such word lines) in the array. Array architecture is discussed in greater detail hereinbelow.
Regarding “reading” the contents of a memory cell, no “injection mechanism” is used. The conventional technique of reading conductive floating gate memory cells is to apply appropriate “read voltages” to the gate and drain and to ground the source. This is similar to the method of programming with the difference being that lower level voltages are applied during reading than during programming.
Since the floating gate is conductive, the trapped charge is distributed evenly throughout the entire floating conductor. In a programmed device, the threshold is therefore high for the entire channel and the process of reading becomes symmetrical. It makes no difference whether voltage is applied to the drain and the source is grounded or vice versa.
The following table presents exemplary conditions for programming, erasing and reading a floating gate memory cell.
TABLE 1Exemplary Floating Gate Operating ConditionsVsVgVdVbtimeErase (FN)>=0 V−8-10 V>=0 V6-8 V100 msProgram (CHE)gnd 8-10 V4-5 V 0 V 1 μsRead 0 V  5 V 1 VProgramming, Erasing and Reading the NROM Cell
NROM cells may be programmed in a manner similar to that of the floating gate memory cell, by injection of channel hot electrons into the charge storage areas (321, 323) of the ONO stack.
FIGS. 3A and 3B illustrate a technique for programming an NROM memory cell, using channel hot electron (CHE) injection to inject electrons into the charge storage areas 321 and 323. As shown in FIG. 3A, the NROM memory cell comprises a channel region between two spaced-apart diffusion regions (left and right), and an ONO stack (322, 324, 326) between the channel region and the gate (328). (Compare FIG. 3.)
Generally, NROM memory cells may be programmed similarly to floating gate memory cells, using a channel hot electron (CHE) injection mechanism. Voltages are applied to the gate and drain creating vertical and lateral electrical fields which accelerate electrons from the source along the length of the channel. As the electrons move along the channel some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer 322 (of the ONO layer) and become trapped in the silicon nitride (charge trapping) layer 324 (of the ONO layer).
The NROM cell can store charges in two separate portions 321 and 323 of the charge-trapping layer 324. For purposes of this portion of the discussion, the left region 321 stores a left bit, and the right region 323 stores a right bit. Depending on which bit (storage region) is desired to be programmed, the left and right diffusion regions 314 and 316 can act as source and drain, or as drain and source. The gate always functions as the gate.
FIG. 3A illustrates CHE programming of the right bit storage area 323. In this example, electron trapping occurs in a region near the diffusion region 316 acting as a drain, as indicated by the dashed circle 323. Electrons are trapped in the portion 323 of nitride layer 324 near but above and self-aligned with the drain region 316 because the electric fields are the strongest there. Thus, the electrons have a maximum probability of being sufficiently energized to jump the potential barrier of the oxide layer 322 and become trapped in the nitride layer 324 near the drain 316.
FIG. 3B illustrates CHE programming of the left bit. For the left bit, the situation is reversed from programming of the right bit. In simple terms, the left diffusion area 314 functions as the drain and the right diffusion area 316 functions as the source, and electrons are sufficiently energized to jump the potential barrier of the oxide layer 322 and become trapped in the nitride layer 324 near the drain 314.
In this disclosure, programming is defined as inserting electrons into the charge trapping areas of an NROM cell to represent data. Generally, more electrons in the charge trapping area creates a higher threshold voltage (Vt). A Vt higher than a threshold level may be considered to represent a binary “0”, and a Vt lower than the threshold level may be considered to represent a binary “1”. Generally, two threshold levels are used for SLC operation. Additional thresholds are used for MLC operation. The threshold Vt should not be confused with the initial Vt of the cell that will be typically lower than the threshold that determines the transition level from a “0” to a “1”.
Generally, to erase a charge-storage area—lowering its Vt—electrons must be removed, or cancelled out, and various mechanisms are known to effect these measures.
For example, in a floating gate memory cell, Fowler-Nordheim tunneling (FNT) is commonly used to extract electrons from the floating gate, thereby lowering the Vt of the memory cell. See FIG. 2B.
For example, in a NROM memory cell, hot hole injection (HHI) is commonly used to cancel electrons in the charge-storage areas. See FIGS. 3C and 3D.
Generally, NROM memory cells may be erased using a technique called hot hole injection (HHI), or tunnel enhanced hot hole (TEHH) injection. For example, to erase an NROM memory cell, the source voltage can be set to a positive voltage such as +5 v, the gate voltage can be set to a negative voltage such as −7 v, and the drain voltage may be set to a positive voltage such as +2 volts (less than the source voltage) or may be left floating or disconnected.
Using HHI, holes (the “counterpart” of electrons) can be selectively inserted into the left portion 321 of the nitride layer 324 and into the right portion 323 of the nitride layer 324, in a controlled manner. Generally, holes which are injected cancel out electrons which are trapped (stored) in the left and right portions of nitride layer on a one-to-one basis (one hole “cancels out” one electron).
FIG. 3C illustrates erasing the right bit storage area. In this example, hole injection (HHI) occurs in a region near the diffusion region 316 acting as a drain, as indicated by the dashed circle 323. Holes are injected in the portion 323 of nitride layer 324 near but above and self-aligned with the drain region 316 because the electric fields are the strongest there. Thus, the holes have a maximum probability of being sufficiently energized to jump the potential barrier of the oxide layer 322 and become injected into the nitride layer 324 near the drain 316.
FIG. 3D illustrates HHI erasing of the left bit storage area. For the left bit storage area, the situation is reversed from erasing of the right bit storage area. In simple terms, the left diffusion area 314 functions as the drain and the right diffusion area 316 functions as the source, and holes are sufficiently energized to jump the potential barrier of the oxide layer 322 and become injected into in the nitride layer 324 near the drain 314.
“Reading” an NROM Cell
Reading an NROM memory cell may involve applying voltages to the terminals of the memory cell comparable to those used to read a floating gate memory cell, but reading may be performed in a direction opposite to that of programming. Generally, rather than performing “symmetrical” programming and reading (as is the case with the floating gate memory cell, described hereinabove), the NROM memory cell is usually programmed and read “asymmetrically”, meaning that programming and reading occur in opposite directions. This is illustrated by the arrows in FIG. 3. Programming is performed in what is termed the forward direction and reading is performed in what is termed the opposite or reverse direction. For example, generally, to program the right storage area 323, electrons flow from left (source) to right (drain). To read the right storage area 323 (in other words, to read the right “bit”), voltages are applied to cause electrons to flow from right to left, in the opposite or reverse direction. For example, generally, to program the left storage area 321, electrons flow from right (source) to left (drain). To read the left storage area 321 (in other words, to read the left “bit”), voltages are applied to cause electrons to flow from left to right, in the opposite or reverse direction. See, for example, commonly-owned U.S. Pat. No. 6,768,165.
Modes of Operation for an NROM Cell
The following table presents exemplary conditions for programming, erasing and reading an NROM memory cell.
TABLE 2Exemplary NROM Operating ConditionsVsVgVdVbtimeProgram (CHE)+0.5 V8-10 V +4-5 V  0 V0.1-1μsErase (HHI)  2 V−7 V5 V0 V100usRead 1.3 V 5 V0 V0 V10-100ns
“Vs” refers to the left diffusion area, and “Vd” refers to the right diffusion area, for the operations of programming, erasing and reading the right side bit of an NROM memory cell. The operations of program and erase are typically performed using pulses, each pulse partially moving (nudging) the memory cell towards the desired Vt, followed by verify (a quick read, to see if the desired Vt has been reached), until the desired Vt has been attained. Typically, conditions are established so that only a few (for example, 3-5) pulses are required to program or erase each cell.
Exemplary operating modes for memory cells, using the mechanism of CHE injection for programming a memory cell, and the mechanisms of FNT and HHI for erasing a memory cell have been described, hereinabove. Other and additional mechanisms are known for performing the modes of operation.
Memory Array Architecture, Generally
Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
As discussed hereinabove, each memory cell comprises a first diffusion (functioning as source or drain), a second diffusion (functioning as drain or source) and a gate, each of which has to receive voltage in order for the cell to be operated, as discussed hereinabove. Generally, the first diffusions (usually designated “source”) of a plurality of memory cells are connected to a first bit line which may be designated “BL(n)”, and second diffusions (usually designated “drain”) of the plurality of memory cells are connected to a second bit line which may be designated “BL(n+1)”. Typically, the gates of a plurality of memory cells are connected to common word lines (WL).
FIG. 4 illustrates an array of NROM memory cells (labeled “a” through “i”) connected to a number of word lines (WL) and bit lines (BL). For example, the memory cell “e” has its gate connected to WL(n), its source (left hand diffusion) is connected to BL(n), and its drain (right hand diffusion) is connected to BL(n+1). The nine memory cells illustrated in FIG. 4 are exemplary of many millions of memory cells that may be resident on a single chip.
Notice, for example that the gates of the memory cells “e” and “f” (to the right of “e”) are both connected to the same word line WL(n). (The gate of the memory cell “d” to the left of “e” is also connected to the same word line WL(n).) Notice also that the right hand terminal (diffusion) of memory cell “e” is connected to the same bit line BL(n+1) as the left-hand terminal (diffusion) of the neighboring memory cell “f”. In this example, the memory cells “e” and “f” have two of their three terminals connected together.
The situation of neighboring memory cells sharing the same connection—the gates of neighboring memory cells being connected to the same word line, the source (for example, right hand diffusion) of one cell being connected to the drain (for example left hand diffusion) of the neighboring cell—is even more dramatically evident in what is called “virtual ground architecture” wherein two neighboring cells actually share the same diffusion. In virtual ground array architectures, the drain of one memory cell may actually be the same diffusion which is acting as the source for its neighboring cell. Examples of virtual ground array architecture may be found in U.S. Pat. Nos. 5,650,959; 6,130,452; and 6,175,519, incorporated in their entirety by reference herein.
Secondary Electron Injection (SEI)
FIG. 5 (compare FIG. 2) illustrates a typical prior art floating gate memory cell 500 (compare 200). The floating gate memory cell comprises source and drain diffusions 514 and 516, embedded in a substrate 502. Between the source and drain diffusions is a channel region 520. A floating gate “FG” is located above the channel 520, insulated therefrom by tunnel oxide. A control gate “CG” is located above the floating gate, insulated therefrom by interpoly oxide.
Voltage levels on the source (Vs), gate (Vg), drain (Vd) and substrate (Vb) are indicated in the figure.
For most floating gate cells, the standard electron injection mechanism for programming is channel hot election (CHE) injection (sometimes abbreviated as CHEI), in which the source to drain potential drop creates a lateral field that accelerates a channel electron e1 from the source S to the drain D, as indicated by the arrow A. Near the drain 516, the high energy electrons e1 may be injected into the floating gate FG, provided that the gate voltage (Vg) creates a sufficiently great vertical field. Typical conditions for CHE injection of electrons into the floating gate of a floating gate memory cell have been discussed, above. (See Table 1. Exemplary Floating Gate Operating Conditions)
Another injection mechanism can occur, known as secondary electron injection (SEI), or simply “secondary injection”. Some of the channel electrons (e1), as they accelerate from source to drain, impact valence electrons in the channel, ionizing the valence electrons, and resulting in the generation (creation) of electron/hole pairs. This is illustrated by the arrow B extending into the drain region 516, and the creation of an electron e2 and a hole h2. The probability of this occurring ionization is denoted M1 and it indicates the ratio between the channel current and the hole substrate current. The circle around M1 is representative of ionization occurring and, although (for illustrative clarity) M1 is shown in the drain 516, it should be understood that this impact ionization (of e1, resulting in e2/h2) occurs in the channel 520, next to the drain 516 or inside the drain 516 close to the channel.
Due to the positive potential (Vd) of the drain 516, generated electrons e2 may be collected by the drain 516, as indicated by arrow C. However, as indicated by the arrow D, generated holes h2 may accelerate towards the low substrate potential Vb of the substrate 502, back under the channel region 520.
In the substrate 502, another impact ionization may occur, this time between holes h2 and valence electrons, creating another electron/hole pair e3, h3 with probability M2. (The circle around M2 is representative of ionization occurring.) Holes h3 are pulled (arrow E) further into substrate 502, and are of no further concern. However, electrons e3, called secondary electrons, may be accelerated (arrow F) towards the positive gate potential Vg of the control gate and, if they have gained sufficient energy, they can be injected into the floating gate—the probability of this occurring being denoted as T. (Electrons e2 are also considered to be impact ionization electrons, but are not of interest since they have low energy and are not candidates for injection.)
Typical conditions for injection of secondary electrons e3 into the floating gate of a floating gate memory cell are shown in the following table.
TABLE 3Exemplary Floating Gate Secondary Injection ConditionsVsVgVdVbtimeSecondary0 V5 V4 V−2 V10 μsInjection
The current (Is) for secondary injection is defined as:IS=Ids×M1×M2×T wherein Ids is the channel current from source to drain.Enhancing Secondary Injection in Floating Gate Cells
Because this current is significant, some floating gate devices have been built to enhance it, thereby reducing programming time and programming voltages. The following articles discuss some possible methods to enhance the secondary injection:                J. D. Bude, et al., “Secondary Electron Flash—a High Performance, Low Power Flash Technology for 0.35.mu.m and Below”, IEDM 97, pp. 279-282;        J. D. Bude, et al., “EEPROM/Flash Sub 3.0V Drain-Source Bias Hot Carrier Writing”, IEDM 95, pp. 989-992; and        J. D. Bude and M. R. Pinto, “Modeling Nonequilibrium Hot Carrier Device Effects”, Conference of Insulator Specialists of Europe, Sweden, June 1997.        
The J. D. Bude references disclose enhancing the secondary generation and injection in two ways: (i) by means of pocket implants of boron (an electron acceptor dopant) in the substrate, and (ii) by applying a negative substrate bias Vb to the substrate. (See, for example, FIGS. 2A and 2B of U.S. Pat. No. 6,429,063.
Boron pockets, when implanted with relatively high energy, enhance the field in the substrate and enhance the creation of the electron-hole pairs e3/h3, and thus increase the probability M2 of secondary electron (e3) generation. This higher boron concentration is effective also in accelerating secondary electrons and hence, enhances their probability T of injection.
The potential drop Vdb from drain to substrate is typically larger by 1 V than the potential drop Vds from drain to source due the built-in potential (Vbi) in the n+/p− substrate junction. This enhances both the probability M2 of a secondary impact and the probability T of injection. To further enhance secondary injection, a negative substrate bias Vb can be applied to the substrate.
The energy balance for secondary injection is a function of the drain voltage Vd (which defines the voltage in the channel), the built-in potential Vbi, the substrate voltage Vsub and the energy Desec after impact ionization. This compares to the primary electron injection mechanism (of channel hot electron injection) which is a function of the drain to source voltage Vds.
Typically, if the drain to source voltage Vds is 3 V and the substrate voltage is at 0 V (and the potential drop from drain to substrate is 1 V), the primary electrons (e1) are accelerated by 3 V while the secondary electrons are accelerated by 4 V. If the substrate voltage is decreased to −1 V, then the secondary electrons are accelerated by 5 V. Thus, applying negative voltage to the substrate increases the secondary injection mechanism.
This energy, when combined with the acceleration of secondary electron e3 over several volts of substrate to channel potential towards gate 112, makes the probability of injection T of secondary electron e3 higher than that of primary electron e1. However, there are many more primary electrons e1 available than secondary electrons e3 and thus, most of the injection remains the primary electrons e1. Since the injected electrons (primary and secondary) spread out in floating gate, there is no way to tell where injection occurred.
When the source/substrate voltage Vbs is decreased to −1.0V the potential energy into substrate increases, although the potential energy in the drain and across the channel does not change. The increased substrate potential provides additional energy to secondary electrons e3 while only slightly affecting the energy of channel electrons e1 through field distribution small changes.
Secondary injection adds to the primary injection mechanism to provide a faster and/or lower voltage injection into a floating gate cell. However, it has heretofore been believed that secondary injection is not good for all types of cells, and that there are some cells, such as nitride, programmable read only memory (NROM) cells, for which enhancing secondary injection appeared to degrade the reliability of the cell. See, for example, U.S. Pat. Nos. 6,429,063 and 6,583,007 for a more detailed discussion of secondary injection in NROM cells.
Reference is made to the following articles, each of which is incorporated by reference in its entirety herein:
Secondary Electron Flash—a High Performance Low Power Flash Technology for 0.35 um and Below, Bude, Mastraopasqua, Pinto, Gregor, Kelley, Kohler, Leung, Ma, McPartland, Roy, Singh, IEEE, 0-7803-4100-7/97, 1997. This article discusses secondary electron injection in a floating gate cell having 7.5 nm tunnel oxide, and suggests that peak CHISEL programming current may be more than 10 times smaller than typical CHE currents (in stacked gate cells).
CHISEL Flash EEPROM—Part I: Performance and Scaling, Mahapatra, Shukuri, Bude, IEEE Transactions on Electron Devices, Vol. 49. No. 7, July 2002. This article discusses secondary electron injection in a floating gate cell, and suggests that under favourable conditions, CHISEL can completely overcome CHE injection in terms of density of electrons injected into the gate electrode.
CHISEL Programming Operation of Scaled NOR Flash EEPROMs—Effect of Voltage Scaling, Device Scaling and Technological Parameters, Mohapatra, Nair, Mahapatra, Rao, Shukuri, Bude, IEEE Transactions on Electron Devices, Vol. 50. No. 10, October 2003. This article discusses secondary electron injection in a floating gate cell, and suggests that CHISEL may provide a higher programming efficiency when compared against conventional CHE operation.
Although these articles suggest that CHISEL (secondary electron injection) can be a valuable mechanism for injecting electrons, better than CHE, they fail to take into account factors relevant to memory cells such as NROM memory cells, having two separate charge storage areas in a single charge storage medium, as the articles are directed to floating gate memory cells where the charge storage medium is a conductor, electrons are free to move around, and it generally does not matter where (within the charge storage medium) the electrons are injected. In contrast thereto, the issue of where (within the charge storage medium) the electrons are injected is of paramount concern in NROM memory cells.
Consider, for example, an extreme case where when trying to program (by injecting electrons into) the right charge storage area (323), electrons were also to be injected into the left charge storage area (321). (This would be a major “2nd bit” event.) In less extreme cases, as will be discussed hereinbelow, electrons which are injected far from the junction (but not so far as to be in the other charge storage area) still present serious problems, for example with read sensitivity, and retention (inability to erase electrons far from the junction).
Managing (Reducing) Secondary Injection in NROM Cells
The phenomenon of the generation of secondary electrons and their injection into the charge storage areas (see 321, 323, FIG. 3) of NROM memory cells has been recognized. The following commonly-owned patents are specifically referenced:
U.S. Pat. No. 6,429,063 (filed Mar. 6, 2000), entitled NROM Cell With Generally Decoupled Primary and Secondary Injection (hereinafter referred to as the '063 patent), and
U.S. Pat. No. 6,583,007 (filed Dec. 20, 2001), entitled Reducing Secondary Injection Effects (hereinafter referred to as the '007 patent).
At the time when these two patents were filed, it was believed that secondary injection was detrimental to the operation of NROM cells.
The '007 patent discloses methods and apparatus for managing and reducing effects of secondary injection in non-volatile memory (NVM) devices that have a non-conducting charge trapping layer, such as NROM devices, and also discloses methods and apparatus for preventing punch-through voltages from detrimentally affecting erase operations in the NVM device that has a non-conducting charge trapping layer.
As disclosed in the '007 patent, generally, movement of secondary electrons from substrate towards the ONO layer (which is also towards the gate) may be managed and may be reduced by controlling a concentration of an electron acceptor dopant in substrate. For example, reducing the presence of the electron acceptor dopant (such as boron) generally near an upper surface of substrate (that is, near the interface between the substrate and the bottom oxide layer of the ONO stack) may significantly reduce secondary electron injection in the direction towards the ONO stack and the polysilicon gate.
As disclosed in the '007 patent, the surface concentration of the electron acceptor dopant may be reduced and the concentration increased far from the upper surface of substrate by one or several methods. For example, the substrate may be constructed with a double or triple implant process. The electron acceptor dopant may be concentrated as a function of depth in the substrate. The electron acceptor dopant may be doped by means of a deep or medium-depth pocket implant (see FIG. 2 of the '007 patent). The surface concentration of the electron acceptor dopant may be reduced by doping the surface with an electron donor dopant (indicated generally in FIG. 2 of the '007 patent), such as, but not limited to, phosphor or arsenic. Although the presence of the electron acceptor dopant deep in the substrate may not reduce the probability M2 of creating electron-hole pairs e3-h3 (see FIG. 1 of the '007 patent, or FIG. 5, herein), nevertheless the distance of the dopant from the upper surface of substrate and far from the n+ junctions and will reduce the probability T of secondary injection, and reduce punch-through.
FIG. 3 of the '007 patent illustrates one example of a concentration of the electron acceptor dopant, such as boron, in terms of depth in the substrate of the NVM device. The boron is concentrated at least 1×1017 cm−2 at a depth of 0.1 μm from the upper surface of the substrate and deeper (for example, but not necessarily, to a depth of about 0.8 μm). At a depth of less than 0.1 μm, the boron concentration is less than 1×1017 cm−2.
As disclosed in the '007 patent, the concentration of the electron acceptor dopant deep in the substrate may reduce punch-through (which is generally undesirable in erase operations on the memory device) deep in the substrate. Surface punch-thorough may be reduced in erase operations by using relatively high negative gate voltages (such as in the range of −5 to −7 V) and relatively low bit line (e.g., drain) voltages to erase the memory device.
The '063 patent discloses techniques for decoupling injection of channel hot electrons into a charge trapping layer of an NROM cell from injection of non-channel (secondary) electrons into the charge trapping layer, as well as for minimizing the generation of the non-channel (secondary) electrons.
The '063 patent discloses that secondary injection reduces the performance of NROM cells because secondary electrons are injected far from the bit line junctions. These secondary electrons are not removable during erasure and thus, reduce the ability of the NROM cell to separate between the two charge storage areas.
Therefore, the '063 patent discloses decoupling the primary (CHE) injection mechanism from other injection mechanisms, such as secondary injection, and enhancing the primary mechanism while reducing the other injection mechanisms. In the '063 patent, secondary electrons (e3) are referred to as “non-channel electrons”.
The '063 patent discloses a method of creating a nitride, programmable read only memory (NROM) cell including the step of decoupling injection of channel hot electrons into a charge trapping layer of the NROM cell from injection of non-channel electrons into the charge trapping layer.
In the '063 patent, the step of decoupling can include the step of minimizing the injection of the non-channel electrons into the charge trapping layer. Alternatively, it includes the step of minimizing the generation of the non-channel electrons.
The step of injection minimization includes at least one of the following steps: minimizing the concentration of Boron deep in the substrate, implanting a shallow threshold voltage implant, implanting deep bit lines and making the channel to be shorter than a standard length.
The NROM cell has at least one Boron pocket implants and the step of Boron concentration reduction includes the step of implanting Arsenic or Phosphorous pocket implants deeper than the Boron pocket implants.
A threshold voltage implant step includes the step of implanting two threshold voltage implants, a first surface implant of Boron and a second deeper implant of Arsenic or Phosphorous. Additionally, Boron pockets can be implanted.
The step of generation minimization includes at least one of the following steps:                minimizing the concentration of Boron deep in the substrate,        implanting a shallow threshold voltage implant, and        making the channel to be shorter than a standard length.        
The NROM cell can include a shallow threshold voltage implant at least of Boron into the channel. The concentration of the Boron is reduced by a factor of 2 at least a distance of 10-20, 20-30, 30-40 and 50-100 nm from a surface of the channel.
The '063 patent goes into great detail to explain how secondary electrons that are injected far from the bit line junctions can cause early failure of the NROM cells, because these secondary electrons are not removable during erasure and thus, they reduce the ability of the NROM cell to withstand a large number of program and erase cycles.
The '063 patent recognizes that the secondary electrons are mainly produced deep in substrate while primary electrons are produced near the surface of substrate, and attempts to decouple the two processes by affecting either the generation of the secondary electrons or by affecting the injection efficiency T, or by enhancing the primary injection while not enhancing the secondary injection to improve the ratio of the primary to secondary injections.
One solution set forth in the '063 patent (see, for example, FIG. 6A therein) is to control the boron concentration into substrate. Generally, the boron concentration is significantly reduced at about 0.5 μm from the surface of the substrate, so that fewer secondary electrons will be generated because there is little or no boron in the areas where secondary electron generation occurs.
In the '063 patent, arsenic or phosphorous (both of which are n+, “electron donors”) is diffused deep into the substrate to counteract the secondary electron generating effects of boron (which is p−, “electron acceptor”). Arsenic or phosphorous, being n+, cancel the effect of the Boron (which is p−) deep in the substrate. To aid the primary injection, the boron remains present near the surface, but little boron, if any, is present deep in the substrate where secondary electrons are produced.
The '063 patent discloses (see, for example, FIGS. 10A, 10B and 10C) enhancing the surface of the channel to improve the primary (CHE) injection mechanism without improving the secondary injection mechanism. The surface enhancement may be provided by a shallow threshold voltage Vt implant of boron. The cell can be produced without a pocket implant, or with a pocket implant. A double threshold voltage implant is shown.
The '063 patent discloses a threshold voltage Vt implant which is produced after the low voltage gate oxide growth step. The Vt implant comprises boron at 3-5×1012/cm2 at 25 KeVand at an angle of 7 degrees. The threshold voltage Vt implant is a shallow implant since it occurs at the end of the high temperature processes and thus, does not have much chance to diffuse into channel. The result is an implant that is more concentrated near a surface of channel, and less concentrated further into the substrate.
The '063 patent discloses having two threshold voltage Vt implants. The first implant is a shallow implant of boron (electron acceptor). The second implant is a deep implant of arsenic or phosphorous (election donor). This “counterdoping” ensures that the boron implant extends only to a known depth. Techniques for performing these shallow and deep implants are discussed.
The '063 patent discloses adding boron pockets to the boron shallow implant. The shallow implant provides the desired surface concentration. The boron pockets add to the surface concentration and provide boron somewhat deeper into substrate. Since the shallow implant provides the desired surface concentration, the boron concentration can be reduced, to at least half that of the previous pockets. Thus, the deep concentration of boron is minimal. Techniques for performing the shallow implant and the pocket implant are discussed.
The '063 patent also discloses having a deeper junction and/or a shorter channel length Leff. Deeper junctions will collect most of the secondary electrons before they get to the surface, thus fewer secondary electrons will be injected into the charge trapping (nitride) layer. A shorter channel has a larger lateral field, for the same drain to source voltage Vds, and thus, the primary (CHE) injection is increased, without increasing the secondary generation, thus, the shorter channel reduces the probability T of injection of secondary electrons into nitride layer.
Related Issues
Although not specifically directed to dealing with problems associated with secondary electron injection (SEI), a technique for decreasing charge distribution and diffusion during and after CHE injection is discussed in Scalable 2-bit silicon-oxide-nitride-oxide-silicon (SONOS) memory with physically separated local nitrides under a merged gate, Lee et al., (Samsung), Solid State Electronics 48 (2004), pp 1771-1775. Generally, the nitride layer (the whole ONO stack) is formed in two distinct sections (may be referred to as “strips”, or “stripes”), rather than as one single planar structure, under the gate. Although the “brute force” approach discussed in the article may provide good 2 bit separation (for either CHE or SEI), it is a complicated structure which may result in a non-uniform (thickness) ONO stack.
A technique for reducing buried bitline resistance is set froth in U.S. patent Publication No. 2006/0084219 (published Apr. 20, 2006) which discloses an NROM structure and method of fabrication (hereinafter referred to as the '219 patent). Polysilicon columns are formed on top of an oxide-nitride-oxide (ONO) layer (stack), and function as gates for memory cells. Spacers are formed on the sides of the polysilicon columns. Bit line (or bitline) diffusions are implanted into the substrate between the spacing elements, and function as source and drain for the memory cells.
The '219 patent discloses implanting a pocket implant such as of boron or indium next to or under the polysilicon columns. An exemplary pocket implant may be of 1-3×1013/cm2 at an angle of 0-15 degrees.
In a virtual ground array (VGA) architecture, such as disclosed in the '219 patent, a given bitline may serve as the drain (or source) of one cell and as the source (or drain) of an adjacent cell. And, a given wordline may serve as the gate electrode for the two adjacent cells.
Commonly-owned patents disclose structure and operation of NROM and related ONO memory cells. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,768,192 and 6,011,725, 6,649,972 and 6,552,387.
Commonly-owned patents disclose architectural aspects of an NROM and related ONO array, (some of which have application to other types of NVM array) such as segmentation of the array to handle disruption in its operation, and symmetric architecture and non-symmetric architecture for specific products, as well as the use of NROM and other NVM array(s) related to a virtual ground array. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,963,465, 6,285,574 and 6,633,496.
Commonly-owned patents also disclose additional aspects at the architecture level, including peripheral circuits that may be used to control an NROM array or the like. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,233,180, and 6,448,750.
Commonly-owned patents also disclose several methods of operation of NROM and similar arrays, such as algorithms related to programming, erasing, and/or reading such arrays. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,215,148, 6,292,394 and 6,477,084.
Commonly-owned patents also disclose manufacturing processes, such as the process of forming a thin nitride layer that traps hot electrons as they are injected into the nitride layer. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,966,603, 6,030,871, 6,133,095 and 6,583,007.
Commonly-owned patents also disclose algorithms and methods of operation for each segment or technological application, such as: fast programming methodologies in all flash memory segments, with particular focus on the data flash segment, smart programming algorithms in the code flash and EEPROM segments, and a single device containing a combination of data flash, code flash and/or EEPROM, Some examples may be found in commonly-owned U.S. Pat. Nos. 6,954,393 and 6,967,896.
A more complete description of NROM and similar ONO cells and devices, as well as processes for their development may be found at “Non Volatile Memory Technology”, 2005 published by Saifun Semiconductor and materials presented at and through http://siliconnexus.com, both incorporated by reference herein in their entirety.